SAN JOSE -- Cypress Semiconductor Corp. here today announced plans
to offer a new series of devices that mix programmable logic and serial
interface functions for high-bandwidth communications applications.
Cypress said its new family of programmable serial interface chips,
called PSI, will reduce system development, complexity and cost.
According to Cypress, the PSI devices will mix programmable logic
with a serializer/deserializer (SERDES) function, a high-speed serial
interface, communications memory, logic and phase-locked loops (PLLs).
The San Jose chip company also said its Warp software will enable
a seamless programming interface for integration of custom intellectual
property (IP) with the SERDES.
first members in the new PSI series will become available in 2001,
and these devices will enable customers to "integrate their logic
IP with our communications devices," said Geoff Charubin, director
of marketing at Cypress.
The company said the PSI chips will provide a programmable interface
to a SERDES that's compatible with various physical layer transmission
media, such as fiber optic modules, copper cables and circuit board
traces. Cypress managers said the combined serial bandwidth of 200
megabits per second to 12 gigabits per second will allow PSI devices
to meet the requirements of a broad range of market segments, including
Gigabit Ethernet, InfiniBand, Fibre Channel, and SONET. The devices
will be housed in ball-grid array (BGA) packages.
backplanes traditionally employ parallel buses; however, designers
aiming to meet the demand for bandwidth in networking systems have
encountered the speed, noise and scalability limitations of this
bus architecture," said Richard Kapusta, senior product marketing
manager at Cypress. "Serial connections, on the other hand, eliminate
cross-talk while increasing system speed, reducing noise and providing
scalability. Serial connections also enable high-speed box-to-box
communication. In addition, system reliability and serviceability
are greatly enhanced."