ARM AXI System Components target SoC designs

Posted : 16 Jun 2004

ARM has begun licensing a set of three IP system components for its ARM11-class processor cores that use the AMBA AXI bus interface specification. Together, the new component cores form a backplane from the CPU core through the cache and memory controllers, to external memory.

The new pre-verified, configurable AXI System Components consist of the L220 AXI Level-2 cache controller, the PL300 AXI configurable interconnect and the PL340 AXI SDRAM controller. ARM is targeting consumer and wireless devices for the system solutions. The components are offered as PrimeCell peripherals, the ARM library of re-usable soft IP macrocells, which enable the rapid assembly of SoC designs.

"Ongoing consumer demand for increased performance in such applications as mobile multimedia and digital TV has led to more complex systems and the need for dramatic in-system performance gains," said John Cornish, director of Product Marketing, ARM. "We have solved this issue with the AXI System Components, which unleash the full benefits of high-frequency processors by optimizing memory system performance."

The L220 Level-2 Cache Controller typically increases system performance by between 50 percent to over 100 percent, by storing recently-used data in high-speed on chip memory. It decreases overall system power consumption by reducing the number of power-hungry external memory accesses, and can enable the use of a less costly memory system.

The PL300 Configurable Interconnect provides a multilayer topology that guarantees the necessary bandwidth and low latency for all connected IP blocks. The interconnect has a throughput of 1.6GB per master at 200MHz and no limitation on the number of masters used. It comes with an XML machine-readable specification that enables easy integration into SPIRIT standard-based EDA tools and drives the configuration of the AXI Configurable Interconnect to the specific requirements of the AXI backplane.

The PL340 SDRAM Controller is the first memory controller to exploit the performance of the AXI backplane and provides up to 1GBps of bandwidth with 32-bit DDR SDRAM. It supports a wide range of memory types including Mobile-DDR, DDR, Mobile SDR and SDR memories. With its configurable architecture, it is possible to select the optimum balance of cost, size and performance to meet system requirements.

The three new products offer additional benefits to consumers, OEMs and ARM silicon partners, according to Cornish. For example, through support of the AMBA AXI interface standard, consumers will not only benefit from longer battery life due to support for the ARM Intelligent Energy Manager (IEM) technology, but also from higher data throughput, which enables software to run faster on end-user equipment. OEMs will reduce costs due to the ability to use less costly off-chip memories. Semiconductor manufacturers will have lower costs through a royalty-free business model for the AXI System Components and fast and reliable design-in. This is achieved through compatibility with the SPIRIT approach and the availability of EDA tools that support SPIRIT.

As well as supporting the ARM1156T2-S processor and the ARM1176JZ-S processor, the AXI System Components support the full performance demands that the new recently launched ARM MPCore multiprocessor can place on a memory sub-system. Using the L220 Cache Controller reduces external memory bandwidth requirements such that a low-cost memory system can be used, such as 32-bit DDR SDRAM while maintaining high system performance. All three of the AXI System Components also support the SPIRIT's XML machine readable specification for easy integration, and for use with tools such as Mentor's Platform Express and Synopsys' coreAssembler.

"In general, the features of AXI technology, such as data bursting, provide a big performance benefit to more advanced, ARM core-based embedded systems. With the addition of these AXI System Components, especially the Level-2 Cache Controller, designers will realize another huge boost in performance for ARM11 family-based processors," said Markus Levy, president, EEMBC. "Using an MPEG4 decode benchmark, similar to the one recently released by EEMBC, ARM was able to demonstrate a 74 percent performance improvement using only a 128k Level-2 cache."

The AXI System Components are available now for licensing on a royalty-free basis. The AMBA AXI interface specification is also royalty-free and can be downloaded by anyone from the ARM website.